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HANBit
HAN BIT
HMS4M16M16G
SRAM MODULE 8Mbyte(4M x 16-Bit) Part No.
HMS4M16M16G
GENERAL DESCRIPTION
The HMS4M16M16G is a high-speed static random access memory (SRAM) module containing 2,097,152 words organized in 4M x16-bit configuration. The module consists of sixteen 1M x 4 SRAMs mounted on a 72pin, double-sided, FR4-printed circuit board. Eight chip enable inputs, (/CE1, /CE2, /CE3 and /CE4) are used to enable the module's 4 bytes independently. Output enable (/OE) and write enable (/WE) can set the memory input and output. Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW. Reading is accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW. For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be powered from a single +5V DC power supply and all inputs and outputs are fully TTL-compatible.
FEATURES
Access times : 10, 12, 15, 17 and 20ns High-density 8MByte design High-reliability, high-speed design Single + 5V 10% power supply Easy memory expansion /CE and /OE functions All inputs and outputs are TTL-compatible Industry-standard pinout FR4-PCB design Low profile 72-pin Part identification
- HMS2M16M8G : SIMM design,Gold
NC NC NC DQ0 DQ1 DQ2 DQ3 Vcc A7 A8 A9 DQ4 DQ5 DQ6 DQ7 /WE A14 /CE1 /CE3 A16 Vss NC NC NC NC A10 A11 A12 A13 NC NC NC NC Vss A19 A20
PIN ASSIGNMENT
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Vcc NC Vss NC DQ8 DQ9 DQ10 DQ11 A0 A1 A2 DQ12 DQ13 DQ14 DQ15 Vss A15 /CE2 /CE4 A17 /OE NC NC NC NC A3 A4 A5 Vcc A6 NC NC NC NC A18
OPTIONS
Timing
10ns access 12ns access 15ns access 17ns access 20ns access
MARKING
-10 -12 -15 -17 -20 M
Packages
72-pin SIMM
Vcc
SIMM/ZIP TOP VIEW
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HANBit Electronics Co.,Ltd.
HANBit
HMS4M16M16G
FUNCTIONAL BLOCK DIAGRAM
DQ0 - DQ15 A0 - A19 A0-A19 /WE U1 DQ0-3 /OE /CE /CE11 A0-A19 /WE U2 DQ4-7 /OE /CE A0-A19 /WE U10 DQ4-7 /OE /CE A0-A19 /WE U9 DQ0-3 /OE /CE
/CE0l
A0-A19 /WE U3 DQ8-11 /OE /CE /CE02 A0-A19 /WE U4 DQ12-15 /OE /CE /CE12
A0-A19 /WE U11 DQ8-11 /OE /CE
A0-A19 /WE U12 DQ12-15 /OE /CE
A-A19 /WE /CE03 /OE
U5 DQ0-3
/CE /CE13
A0-A19 /WE U13 DQ0-3 /OE /CE
A0-A19 /WE U6 /OE
DQ4-7 /CE
A0-A19 /WE U14 DQ4-7 /OE /CE
A0-A19 /WE U7 DQ8-11 /OE /CE /CE04 A0-A19 /WE U8 DQ12-15 /OE /CE /OE /WE /CE14
A0-A19 /WE U15 DQ8-11 /OE /CE
A0-A19 /WE U16 DQ12-15 /OE /CE
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HANBit Electronics Co.,Ltd.
HANBit
HMS4M16M16G
A(20)
74F04
74F32 74F32 74F32 74F32 74F32 /CE3 74F32 74F32 74F32
/LCE1 /HCE1 /LCE2 /HCE2 /LCE3 /HCE3 /LCE4 /HCE4
/CE1
/CE2
/CE4
TRUTH TABLE
MODE STANDBY NOT SELECTED READ WRITE /OE X H L X /CE H L L L /WE X H H L OUTPUT HIGH-Z HIGH-Z DOUT DIN POWER STANDBY ACTIVE ACTIVE ACTIVE
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HANBit Electronics Co.,Ltd.
HANBit
HMS4M16M16G
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN,OUT VCC PD TSTG RATING -0.5V to +7.0V -0.5V to +7.0V 16W -65oC to +150oC
Operating Temperature TA 0oC to +70oC Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage * SYMBOL VCC VSS VIH VIL MIN 4.5V 0 2.2 -0.5*
( TA=0 to 70 o C ) TYP. 5.0V 0 MAX 5.5V 0 Vcc+0.5V** 0.8V
VIL(Min.) = -2.0V ac (Pulse Width 10ns) for I 20 mA
** VIH(Min.) = Vcc+2.0V ac (Pulse Width 10ns) for I 20 mA
DC AND OPERATING CHARACTERISTICS (1)(0oC TA 70 oC ; Vcc = 5V 0.5V )
PARAMETER Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage * Vcc=5.0V, Temp=25 oC TEST CONDITIONS VIN =Vss to Vcc /CE=VIH or /OE =VIH or /WE=VIL VOUT=Vss to VCC IOH = -4.0Ma IOL = 8.0Ma SYMBO L ILI IL0 VOH VOL MIN -2 -2 2.4 0.4 MAX 2 2 UNITS A A V V
DC AND OPERATING CHARACTERISTICS (2)
MAX DESCRIPTION Power Supply Current: Operating Power Supply Current :Standby TEST CONDITIONS Min. Cycle, 100% Duty /CE=VIL, VIN=VIH or VIL, IOUT=0mA Min. Cycle, /CE=VIH f=0MHZ, /CEVCC-0.2V, VIN VCC-0.2V or VIN0.2V SYMBOL lCC lSB lSB1 -10 195 50 10 -12 190 50 10 -15 185 50 10 UNIT mA mA mA
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HANBit CAPACITANCE
DESCRIPTION Input /Output Capacitance Input Capacitance TEST CONDITIONS VI/O=0V VIN=0V SYMBOL CI/O CIN
HMS4M16M16G
MAX 8 7
UNIT pF pF
* NOTE : Capacitance is sampled and not 100% tested
AC CHARACTERISTICS (0oC TA 70 oC ; Vcc = 5V 0.5V, unless otherwise specified)
TEST CONDITIONS PARAMETER Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load VALUE 0 to 3V 3ns 1.5V See below
Output Load (A) VL=1.5V 50 DOUT Z0=50 30pF DOUT 255
Output Load (B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5.0V 480 5pF*
READ CYCLE
-10 PARAMETER Read Cycle Time Address Access Time Chip Select to Output Output Enable to Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Output Disable to High-Z Output Chip Disable to High-Z Output Output Hold from Address Change Chip Select to Power Up Time
SYMBOL MIN MAX MIN MAX MIN MAX
-12
-15
UNIT
tRC tAA tCO tOE tLZ tOLZ tOHZ tHZ tOH tPU
10 3 0 0 0 3 0
10 10 5 5 5 -
12 3 0 0 0 3 0
12 12 6 6 6 -
15 3 0 0 0 3 0
15 15 7 7 7 -
ns ns ns ns ns ns ns ns ns ns
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HANBit
Chip Select to Power Down Time tPD 10 12
HMS4M16M16G
15 ns
WRITE CYCLE
-10 PARAMETER Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width (/OE High) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End of Write to Output Low-Z
SYMBOL MIN MAX MIN MAX MIN MAX
-12
-15
UNIT
tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW
10 7 0 7 7 0 0 5 0 3
5 -
12 8 0 8 8 0 0 6 0 3
6 -
15 10 0 10 10 0 0 7 0 3
7 -
ns ns ns ns ns ns ns ns ns ns
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE( Address Controlled)( /CE =/OE = VIL , /WE = VIH)
tRC Address tAA tOH Data out
Previous Data Valid Data Valid
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HANBit Electronics Co.,Ltd.
HANBit
HMS4M16M16G
TIMING WAVEFORM OF READ CYCLE ( /WE = VIH )
tRC Address tAA /CE tLZ(4,5) /OE tOLZ Data Out Vcc Supply Current High-Z
Data Valid
tHZ(3,4,5) tCO tOHZ tOE tOH
lCC lSB
tPU 50%
tPD 50%
Notes (Read Cycle)
1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CE = VIL. 7. Address valid prior to coincident with /CE transition low.
TIMING WAVEFORM OF WRITE CYCLE (/OE = Clock )
tWC
Address
tAW tWR(5)
/OE
tCW(3)
/CE
tAS(4) tWP(2)
/WE
tDW tDH High-Z Data Valid tOHZ tOW High-Z
Data In
Data Out
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HANBit Electronics Co.,Ltd.
HANBit
HMS4M16M16G
TIMING WAVEFORM OF WRITE CYCLE (/OE Low Fixed)
tWC
Address
tAW tCW(3) tWR(5)
/CE
tAS(4) tOH tWP(2) tDW tDH Data Valid tWHZ(6,7) tOW High-Z(8) (10) (9)
/WE
Data In
High-Z
Data Out
Notes(Write Cycle)
1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among /CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CE going low to the end of write. 4. tAS is measured from the address valid to the beginning of wirte. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CE, or /WE going high. 6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state. 9. DOUT is the read data of the new address. 10. When /CE is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
/CE H L L L /WE X* H H L /OE X H L X MODE Not Select Output Disable Read Write I/O PIN High-Z High-Z DOUT DIN SUPPLY CURRENT I SB, I SB1 ICC ICC ICC
Note: X means Don't Care
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HANBit Electronics Co.,Ltd.
HANBit
HMS4M16M16G
PACKAGE DIMMENSIONS
SIMM Design
107.95 mm
.125 (3.18) TYP(2x) 3.38 mm 26.49 mm
10.16 mm
1
10.16 mm 72
2.0 mm 1.02 mm 6.35 mm 1.27 mm 3.38 mm
6.35 mm
95.25 mm
6.35 mm
0.25 mm MAX
2.54 mm MIN
Gold: 1.040.10 mm 1.27 Solder: 0.9140.10 mm
1.29 0.08mm
(Solder & Gold Plating Lead)
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HANBit Electronics Co.,Ltd.
HANBit
HMS4M16M16G
ODERING INFORMATION
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5
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HMS
HANBit Memory Modules SRAM
4M 16 M 16G -15
15ns Access Time Component, Gold SIMM X16bit 4M
1. - Product Line Identifier HANBit ------------------------------------------------------ H 2. - Memory Modules 3. - SRAM 4. - Depth : 4M 5. - Width : x 16bit 6. - Package Code SIMM ------------------------------------------------------- M 7. - Number of Memory Components - 8 , Gold finish lead - G 8. - Access time 10 ----------------------------------------------------------- 10ns 12 ----------------------------------------------------------- 12ns 15 ----------------------------------------------------------- 15ns 17 ----------------------------------------------------------- 17ns 20 ----------------------------------------------------------- 20ns
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